Baud Rate Calculation Formula For Can

Use this interactive CAN bus baud rate calculator to estimate bit rate, bit time, sample point, and timing quanta from common controller timing values. Enter the CAN peripheral clock, baud rate prescaler, and segment values to calculate the effective baud rate using the standard CAN timing relationship.

Formula Baud Rate = CAN Clock / (Prescaler × Total TQ)

Total TQ 1 + TSEG1 + TSEG2

Sample Point (1 + TSEG1) / Total TQ × 100

Understanding the baud rate calculation formula for CAN

The baud rate calculation formula for CAN is one of the most important timing relationships in embedded networking, automotive electronics, industrial automation, and real time control systems. The CAN protocol, short for Controller Area Network, is built around precise bit timing. Even when the physical bus wiring, transceivers, and termination resistors are correct, communication can still fail if the configured timing values inside the controller do not produce the expected bit rate or sample point. That is why engineers, technicians, and firmware developers often begin debugging a CAN network by verifying the timing formula first.

In practical terms, nominal CAN baud rate is determined by the CAN controller clock, the baud rate prescaler, and the total number of time quanta per bit. The standard engineering expression is:

Baud Rate = CAN Clock / (Prescaler × Total Time Quanta per Bit)

Total Time Quanta per Bit = 1 + TSEG1 + TSEG2

The fixed 1 in the equation represents the synchronization segment, often written as Sync_Seg. The rest of the bit is divided into Time Segment 1 and Time Segment 2. Depending on the controller family, TSEG1 may internally include the propagation segment and phase segment 1, while TSEG2 corresponds to phase segment 2. Some chip vendors use slightly different register naming, but the effective formula remains the same.

Why CAN baud rate matters so much

CAN is designed for robust communication in electrically noisy environments. However, its reliability depends on every node agreeing closely on the length of a bit. If one controller thinks a bit is shorter or longer than another controller expects, sample points drift, edges are misread, and error frames appear. This is why timing design is not just about reaching 500 kbps or 250 kbps on paper. It is also about choosing a practical sample point, acceptable oscillator tolerance, and a speed that matches the physical length of the network.

Higher baud rates reduce transmission latency, but they also tighten timing margins. At lower speeds, each bit is longer in time, making propagation delays across a longer cable easier to tolerate. This tradeoff explains why short automotive subnets often run at 500 kbps or 1 Mbps, while longer industrial lines may run at 125 kbps or below.

The core timing components

• CAN clock: The input clock used by the CAN peripheral. This may be derived from a microcontroller oscillator, PLL, or peripheral bus clock.
• Prescaler: Divides the CAN clock to create the time quantum base period.
• Sync segment: Fixed at 1 time quantum and used to align bit timing to edges.
• TSEG1: Covers propagation delay compensation and the early phase of the bit before the sample point.
• TSEG2: Covers the late phase of the bit after the sample point.
• SJW: The synchronization jump width. It does not change the nominal baud rate, but it affects how much a node may resynchronize based on detected edges.

Step by step baud rate calculation for CAN

Suppose your CAN peripheral clock is 16 MHz, the prescaler is 2, TSEG1 is 13, and TSEG2 is 2. Then the total bit time is:

1. Calculate total time quanta: 1 + 13 + 2 = 16 TQ
2. Calculate time quantum period: Prescaler / Clock = 2 / 16,000,000 = 125 ns
3. Calculate bit time: 16 × 125 ns = 2 microseconds
4. Calculate baud rate: 1 / 2 microseconds = 500,000 bits per second

That yields a nominal baud rate of 500 kbps. The sample point is reached after the sync segment and TSEG1, so:

Sample Point = (1 + TSEG1) / (1 + TSEG1 + TSEG2) × 100

For this example: (1 + 13) / 16 × 100 = 87.5%

An 87.5% sample point is common in many CAN networks because it provides a good balance between propagation delay tolerance and timing stability, especially at moderate speeds such as 125 kbps, 250 kbps, and 500 kbps.

Common CAN speeds and exact bit timing statistics

The table below shows commonly used nominal CAN data rates and their exact bit times. These are useful reference values when selecting timing registers or when checking if an observed waveform on an oscilloscope matches the intended network speed.

Nominal Baud Rate	Bits per Second	Bit Time	Typical Use Case	Approximate Practical Bus Length Guideline
1 Mbps	1,000,000	1.0 microsecond	Short high speed automotive or machine subnet	About 40 m
800 kbps	800,000	1.25 microseconds	High speed short backbone	About 50 m
500 kbps	500,000	2.0 microseconds	Very common automotive and industrial speed	About 100 m
250 kbps	250,000	4.0 microseconds	Mixed industrial and mobile equipment	About 250 m
125 kbps	125,000	8.0 microseconds	Longer control network segments	About 500 m
50 kbps	50,000	20 microseconds	Long low speed systems	About 1000 m
20 kbps	20,000	50 microseconds	Very long and slow field systems	About 2500 m
10 kbps	10,000	100 microseconds	Special long distance low throughput links	About 5000 m

How engineers choose TSEG1 and TSEG2

It is tempting to think only about the final baud rate, but many combinations of prescaler, TSEG1, and TSEG2 can produce the same nominal speed. The real engineering decision comes from selecting values that also produce an appropriate sample point and allow good resynchronization behavior. In many applications, a sample point between about 75% and 87.5% is common. Lower speed networks often favor sample points closer to 87.5%, while very high speed networks may use slightly earlier sample points depending on controller limitations and physical layout.

For example, with a 16 MHz clock and a target of 500 kbps, one valid combination is BRP = 2 and total TQ = 16. Another controller might implement a different internal divider or register encoding, so the datasheet must always be consulted. Some devices store BRP as value minus one, and some represent TSEG values with encoded offsets. Your firmware must convert human timing values into the exact register format expected by the device.

Clock	Prescaler	TSEG1	TSEG2	Total TQ	Resulting Baud Rate	Sample Point
16 MHz	2	13	2	16	500 kbps	87.5%
16 MHz	4	13	2	16	250 kbps	87.5%
16 MHz	8	13	2	16	125 kbps	87.5%
8 MHz	1	13	2	16	500 kbps	87.5%
20 MHz	2	15	4	20	500 kbps	80.0%

Key formula details that people often miss

1. Baud rate is not always equal to oscillator frequency divided by prescaler

The prescaler only creates the time quantum. You must still multiply by the total number of quanta in one bit. Forgetting this leads to baud rate values that are off by a large factor.

2. SJW does not set the baud rate

Synchronization Jump Width affects how far the timing engine can shift phase during resynchronization, but it does not directly change the nominal bit rate equation. Still, SJW matters for robustness, especially when oscillator tolerance and edge placement are imperfect.

3. Sample point is just as important as the final speed

Two timing configurations can both produce 500 kbps, but one may place the sample point much earlier or later than the other. A poor sample point can reduce noise immunity or worsen propagation delay margin.

4. Register encoding can differ from displayed values

Many controllers use encoded register values such as BRP register = actual prescaler minus 1. The same can apply to segment lengths. Always use the silicon vendor documentation before programming registers directly.

How physical network length influences practical baud rate

Signal propagation delay grows with cable length. As the bus becomes longer, the transmitter and receiver need more timing margin before the sample point. That is why lower baud rates are often selected for longer runs. The exact limit depends on cable type, transceiver delay, node count, topology quality, and overall EMC conditions. Even so, there is a widely used practical relationship: as baud rate decreases, permissible bus length increases substantially. The calculator on this page gives you a nominal timing result, but successful deployment still requires checking physical layer design, proper termination, and acceptable oscillator tolerance.

Practical workflow for selecting a CAN timing configuration

1. Determine the CAN peripheral clock available to the controller.
2. Choose the target baud rate based on network throughput and cable length.
3. Select a total number of time quanta per bit that your controller supports.
4. Pick a prescaler that makes the formula produce the target baud rate as closely as possible.
5. Adjust TSEG1 and TSEG2 to reach a reasonable sample point, often near 80% to 87.5%.
6. Select SJW within the controller rules, usually not larger than TSEG2.
7. Validate with an oscilloscope or bus analyzer to confirm the observed bit time and stability.

Example interpretation of calculator results

When you use the calculator above, you receive several outputs. The calculated baud rate tells you the nominal bit rate. Total TQ tells you how many timing quanta make up one bit. Bit time tells you the real duration of each bit on the bus. Sample point shows when the receiver samples the bit relative to the start of the bit. Error versus target baud rate shows whether your register values produce the speed you intended. In production systems, even a small mismatch can matter if it combines with oscillator error from multiple nodes.

Authoritative references and further reading

For broader timing, measurement, and transportation systems context, these sources are useful:

• NIST Time and Frequency Division
• National Highway Traffic Safety Administration
• Carnegie Mellon University Electrical and Computer Engineering

Final takeaways

The baud rate calculation formula for CAN is simple in appearance but powerful in application. Once you know the controller clock, prescaler, and bit segment values, you can compute the exact nominal bit rate and sample point. That allows you to verify whether your firmware settings are correct before you deploy a node to a real bus. The formula is:

Baud Rate = CAN Clock / (Prescaler × (1 + TSEG1 + TSEG2))

If you remember one engineering principle, remember this: do not optimize for speed alone. A good CAN timing setup balances bit rate, sample point, propagation delay margin, and controller capabilities. Use the calculator to test combinations quickly, then confirm them against your microcontroller datasheet and your network’s physical requirements.