A New Calculation For Designing Multilayer Planar Spiral Inductors

Use this premium engineering calculator to estimate inductance, coupling-adjusted multilayer inductance, DC resistance, skin-effect adjusted AC resistance, and quality factor for multilayer planar spiral inductors. The model combines a planar spiral inductance equation with an interlayer coupling approximation suitable for fast early-stage design screening.

This tool uses a fast semi-empirical planar spiral model plus an exponential interlayer coupling term. It is ideal for concept design, stack-up tradeoffs, and screening before full 3D field simulation.

A New Calculation for Designing Multilayer Planar Spiral Inductors

Designing multilayer planar spiral inductors has become increasingly important in compact electronics, wireless power transfer systems, RF front ends, sensing platforms, embedded power modules, and miniaturized resonant networks. Traditional wire-wound inductors still dominate many high-inductance applications, yet modern layouts often demand low-profile components that can be fabricated on printed circuit boards, ceramic substrates, silicon interposers, or advanced package substrates. In those contexts, planar spiral inductors offer a valuable combination of manufacturability, repeatability, and integration. The challenge is that performance depends on more than just turn count. Outer dimension, inner opening, conductor width, spacing, number of layers, copper thickness, interlayer dielectric separation, and operating frequency all interact. A practical designer needs a quick but credible calculation method long before finite element simulation is scheduled.

This page introduces a useful workflow for what can fairly be called a new calculation for designing multilayer planar spiral inductors: start with a proven single-layer planar spiral inductance expression, then extend it with a coupling-aware multilayer stacking model. The result is not intended to replace a full electromagnetic solver. Instead, it helps answer the questions that matter early in design: how much inductance will a stack gain over a single layer, how strongly does dielectric thickness reduce magnetic coupling, when does adding layers stop paying off, and how much quality factor is lost to conductor resistance at the target frequency?

Why multilayer planar spiral inductors matter

A single-layer planar spiral is easy to fabricate, but it reaches geometric limits quickly. If you want more inductance, the usual options are to increase turns, enlarge area, or shrink conductor pitch. Each choice has a cost. More turns increase resistance. A larger footprint conflicts with compact packaging. Narrower conductors raise current density and worsen DC and AC loss. Multilayer stacking creates a different path: by placing spirals above or below one another and connecting them in series aiding fashion, a designer can increase total inductance while preserving much of the lateral footprint.

• Embedded magnetics in compact power converters where height is available inside the stack-up but board area is constrained.
• NFC, RFID, and wireless charging coils that must fit a mechanical envelope without sacrificing field strength.
• MEMS and sensor front-end circuits where a planar process is preferred over discrete wound components.
• Integrated package inductors for RF matching, filtering, and resonant tank networks.

However, multilayer behavior is more complex than simply multiplying single-layer inductance by the number of layers. Adjacent spirals couple magnetically. If connected correctly, this coupling boosts total inductance above the uncoupled series sum. If the spacing is too large, the gain diminishes. If the winding polarity is wrong, coupling can even become subtractive. That is why a coupling-aware estimate is so useful.

The core idea behind this calculation

The method implemented in the calculator combines two pieces. First, it estimates the inductance of one planar spiral layer using a geometry-specific formula based on average diameter and fill factor. Second, it estimates mutual reinforcement between layers with a decaying coupling coefficient. For identical layers connected in series aiding mode, total inductance can be expressed as the sum of self inductance plus twice the mutual inductance between every unique layer pair.

Conceptually: total multilayer inductance is the single-layer self inductance multiplied by the number of layers, plus a coupling bonus created by magnetic interaction among the stacked spirals.

This is a highly practical engineering approximation because it reflects a real physical truth: the magnetic field from one spiral links partially with the turns on nearby layers, and that linkage weakens with separation. The implemented coupling coefficient decays as layer separation increases. In early-stage design this captures the dominant effect surprisingly well.

How the single-layer part works

For a planar spiral, the key geometric quantities are the outer dimension, inner dimension, average diameter, and fill ratio. Average diameter is simply the midpoint between the outer and inner dimensions. Fill ratio is the ratio of conductor spread to average size. Spirals with larger fill factors generally achieve higher inductance for the same outer size, but the resistance penalty can also rise because the total conductor length grows. Geometry also matters. Square spirals are common in PCB design because routing is straightforward. Circular spirals usually provide a smoother current path and slightly different current distribution. Octagonal spirals are often treated as a practical compromise between circular performance and polygon-based manufacturing simplicity.

1. Choose the geometry type: square, octagonal, or circular.
2. Calculate average dimension from outer and inner size.
3. Calculate fill factor from the spread between outer and inner boundaries.
4. Apply the geometry-specific inductance expression to estimate single-layer self inductance.
5. Compute conductor length and resistance from trace width, thickness, and total path length.
6. Use frequency to estimate skin depth and AC resistance.
7. Apply the multilayer coupling model to compute total inductance.

Because the implemented model is fast, it is perfect for comparing many design alternatives in minutes. A full field solver can then be reserved for the best few candidates.

How multilayer coupling changes the answer

In a stacked design, each layer can couple to every other layer. The strongest interaction occurs between immediate neighbors because the field lines have the smallest separation to cross. Layers farther apart still couple, but less strongly. A simple and effective way to capture that trend is to model the coupling coefficient as an exponential decay function of normalized spacing. In practical terms, when dielectric thickness shrinks or average coil diameter grows, coupling tends to increase. When separation becomes a significant fraction of coil size, the coupling contribution drops rapidly.

This matters because the total inductance scaling is not linear in the number of layers. Consider four identical layers. If they were completely uncoupled and connected in series, the total inductance would be four times the single-layer value. But with strong magnetic coupling, the actual total can be materially higher than four times. That gain is one of the biggest reasons multilayer planar inductors are attractive in compact designs.

Parameter	Typical PCB coil range	Typical advanced package range	Design effect
Trace width	0.10 to 1.00 mm	0.015 to 0.100 mm	Wider traces reduce resistance but can limit turns in a fixed area.
Copper thickness	17 to 105 µm	5 to 30 µm	Thicker metal lowers DC resistance and delays AC resistance growth.
Interlayer spacing	0.08 to 0.30 mm	0.005 to 0.050 mm	Smaller spacing increases magnetic coupling and boosts total inductance.
Turns per layer	2 to 15	1 to 8	More turns usually increase inductance faster than area alone, but resistance rises too.
Operating frequency	100 kHz to 30 MHz	1 MHz to 10 GHz	Higher frequency reduces skin depth and may lower effective Q if metal is thin.

Real-world electrical statistics designers should know

Two physical statistics shape practical inductor design more than many layout teams realize. First, the resistivity of copper at room temperature is approximately 1.68 to 1.72 × 10^-8 ohm-meter, depending on purity and temperature assumptions. Second, skin depth in copper falls very quickly with frequency. At 100 kHz it is about 0.206 mm, at 1 MHz about 0.065 mm, at 13.56 MHz about 0.018 mm, and at 100 MHz about 0.0065 mm. These numbers explain why an inductor that looks efficient at low frequency can become surprisingly lossy in RF or near-field applications.

Frequency	Approximate copper skin depth	Implication for common copper thicknesses
100 kHz	206 µm	Standard 35 µm copper is thinner than skin depth, so AC resistance is close to DC resistance.
1 MHz	65 µm	35 µm copper still performs reasonably well, though AC resistance begins increasing.
13.56 MHz	18 µm	35 µm copper exceeds the one-skin-depth region, so effective AC resistance increases notably.
100 MHz	6.5 µm	Only the outer portion of thick copper carries most current, reducing conductor efficiency.
1 GHz	2.1 µm	Surface current dominates and layout parasitics often become as important as nominal inductance.

What this means for practical design decisions

If your target is high inductance in a compact footprint, adding layers can be more effective than simply increasing turns on a single layer. Yet the benefit depends on maintaining strong coupling. That usually means keeping interlayer spacing small relative to average spiral diameter. If your target is quality factor, then conductor width and thickness become critical. There is no point creating a large coupling-enhanced inductance if AC resistance climbs so fast that Q collapses. This is why the calculator reports both inductance and loss-related metrics.

• For NFC and RFID: prioritize footprint efficiency, target inductance window, and manageable AC resistance near 13.56 MHz.
• For power transfer: use wider traces and thicker copper to control current density and resistive heating.
• For sensor resonators: stabilize geometry and dielectric spacing, because repeatability often matters more than absolute peak inductance.
• For package-level RF inductors: monitor parasitics carefully, since distributed capacitance can limit self-resonant frequency.

Advantages of this new calculation approach

The value of this method is speed paired with physical intuition. It reveals the direction and magnitude of major tradeoffs quickly. Increase layers and watch total inductance rise. Increase spacing and see coupling weaken. Increase copper thickness and see resistance improve. Change geometry and compare square, octagonal, and circular forms. These are exactly the questions engineers ask in the early design phase, and they are often the bottleneck before simulation and prototyping resources are committed.

Another advantage is communication. A design review becomes easier when the underlying calculation is understandable. A black-box 3D solver can be authoritative, but it is not always transparent. A semi-empirical model gives electrical, layout, and manufacturing teams a common framework for discussing why one stack-up beats another.

Limitations you should respect

No compact formula captures every effect. This approach assumes each layer is geometrically similar, aligned, and connected in the correct polarity. It does not fully model distributed capacitance, proximity effect among adjacent turns, via parasitics, corner current crowding, anisotropic substrates, ferrite backing layers, or frequency-dependent permeability effects. In high-frequency or high-current designs, those factors can materially alter performance. Therefore, use this calculator as a front-end design tool, not as the final signoff method.

As a best practice, use this workflow:

1. Create three to five candidate geometries with this calculator.
2. Select the most promising design points based on inductance, resistance, and Q.
3. Move those finalists into a 2.5D or 3D electromagnetic simulation environment.
4. Build at least one prototype stack-up to validate real material properties and fabrication tolerances.

Recommended validation references

For deeper technical background and verified physical constants, consult authoritative sources such as the NIST reference on physical constants, MIT OpenCourseWare electromagnetics materials, and the NASA technical resources portal for broader electromagnetic and materials context.

Final takeaway

A new calculation for designing multilayer planar spiral inductors should do more than report a single inductance number. It should connect geometry, layer count, spacing, conductor properties, and frequency into one coherent design story. That is what this calculator aims to provide. By combining a trusted planar inductance estimate with a coupling-aware multilayer extension, it lets designers make fast, informed decisions about compact magnetic structures. Whether you are optimizing for wireless power, resonant sensing, RF integration, or board-level miniaturization, a coupling-aware multilayer estimate is one of the most useful first-pass tools you can have.